Low-Power Deep Sub-Micron CMOS Logic

Low-Power Deep Sub-Micron CMOS Logic

Author: P. van der Meer

Publisher: Springer Science & Business Media

ISBN: 9781402028496

Category: Technology & Engineering

Page: 154

View: 501

Download BOOK ยป

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.
Low-Power Deep Sub-Micron CMOS Logic
Language: en
Pages: 154
Authors: P. van der Meer, A. van Staveren, Arthur H.M. van Roermund
Categories: Technology & Engineering
Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until
Low Power Design in Deep Submicron Electronics
Language: en
Pages: 580
Authors: W. Nebel, Jean Mermet
Categories: Technology & Engineering
Type: BOOK - Published: 2013-06-29 - Publisher: Springer Science & Business Media

Low Power Design in Deep Submicron Electronics deals with the different aspects of low power design for deep submicron electronics at all levels of abstraction from system level to circuit level and technology. Its objective is to guide industrial and academic engineers and researchers in the selection of methods, technologies
Low-Power Deep Sub-Micron CMOS Logic
Language: en
Pages: 172
Authors: P. Van Der Meer, A. Van Staveren, Arthur H M Van Roermund
Categories: Technology & Engineering
Type: BOOK - Published: 2005-08-04 - Publisher:

Books about Low-Power Deep Sub-Micron CMOS Logic
Low Power Deep Sub-micron CMOS Logic
Language: en
Pages: 158
Authors: Paul Robert van der Meer
Categories: Technology & Engineering
Type: BOOK - Published: 2002 - Publisher:

Books about Low Power Deep Sub-micron CMOS Logic
Low-Power CMOS Circuits
Language: en
Pages: 440
Authors: Christian Piguet
Categories: Technology & Engineering
Type: BOOK - Published: 2018-10-03 - Publisher: CRC Press

The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published Low-Power Electronics Design, Low-Power CMOS Circuits: Technology, Logic Design, and CAD Tools addresses the design of low-power circuitry in deep submicron technologies. It provides a